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NXP Semiconductors /LPC5410x /SYSCON /NMISRC

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Interpret as NMISRC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IRQM40RESERVED 0IRQM00RESERVED0 (NMIENM0)NMIENM0 0 (NMIENM4)NMIENM4

Description

NMI Source Select

Fields

IRQM4

The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
RESERVED

Reserved. Read value is undefined, only zero should be written.
IRQM0

The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+, if enabled by NMIENM0.
RESERVED

Reserved. Read value is undefined, only zero should be written.
NMIENM0

Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0.
NMIENM4

Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data